1. Field of the Invention
The present invention relates to a parallel processing control apparatus for controlling a parallel processor that simultaneously processes a plurality of instructions.
2. Description of the Prior Art
Parallel processors employ a parallel processing system such as a superscalar system and a VLIW system, for simultaneously issuing and processing a plurality of instructions. These parallel processors are complicated to control. In particular, the superscalar parallel processor is very complicated because it is usually required to realize upper compatibility to use software of conventional sequential processors and because it is required, when processing instructions, to consider what it might be if the instructions were processed by the conventional sequential processors.
With a development of LSI technology in recent years, processing units such as floating-point processing units, which have been usually fabricated on a separate chip and used with the superscalar parallel processor, are mounted on a single chip with other processing units.
The number of pipeline stages of the floating-point processing units usually differs from those of other processing units, and therefore, the floating-point processing units take a longer processing time. Controlling a plurality of such processing units having different processing times is very difficult for the superscalar system. It is necessary, therefore, to provide a parallel processing control apparatus that efficiently controls processing units involving different processing times.
When parallelly controlling a plurality of processing units involving different numbers of pipeline stages and different processing times, a conventional parallel processing control apparatus sometimes causes an instruction to overtake the preceding instruction if the preceding instruction involves more pipeline stages than the succeeding instruction.
If such an exception of overtaking occurs after the preceding instruction is completely processed, a problem is to determine which instruction must be executed or aborted. If a plurality of instructions are simultaneously completed, there is a problem of selecting one instruction to write its status in a status register.
A write reservation register may be employed to control the order of outputs of a plurality of operation units having different pipeline stages. This, however, increases hardware because many registers for storing values must be prepared to cover a difference between the maximum and minimum numbers of pipeline stages.